1. Field of Invention
The present invention generally relates to a programming and erasing method of flash memory, and more particularly, to a programming and erasing method of multi-level flash memory.
2. Description of Related Art
In the process of programming and erasing a flash memory bit, in order to have the flash memory describe the binary state and the trinity state, or . . . state, (00, 01, 10, 11 state or 000, 001, 010, 011, 100, 101, 110, 111 state, or . . . state), the means of changing the gate voltage of the flash memory periodically is commonly used to limit the number of the gate voltage shooting times, so that the channel of the flash memory is able to generate the channel hot electrons, and the state when the channel hot electrons are injected to the floating gate via the channel can be different. For example, in order to have multi-level flash memory that represents the binary state describing the multi-level state of the binary bit, its floating gate must have the capacity to store electrons with four different electron distribution states. When the flash memory represents the 00 state value, there is an electron distribution corresponding to the 00 state value stored in the floating gate.
The conventional programming method of the flash memory is: when the flash memory programs from state 00 to 01, 10 or 11 state, the gate voltage Vg is shot into the gate of the flash memory. The gate voltage Vg is increased by 0.1 volt every time it is shot into the gate (i.e. ΔVg is 0.1 volt), and is sustained for about 150 ns every time. The programming of flash memory to the 01 or 10 or 11 states from 00 state is determined by the number of times the gate voltage Vg is shot into gate. Where a program verify voltage is carried by the programming voltage in each operation.
When the flash memory is erased to 00 state from 01 or 10 or 11 state, the gate voltage Vg is decreased by 0.5 volt every shot into the gate (i.e. ΔVg is −0.5 volt), and is sustained for about 100˜500 μs every time. The number of times the gate voltage Vg is shot into the gate to erase to 00 state from 01 or 10 or 11 states. Where an erase verify voltage is carried by the erasing voltage in each operation.
Referring to FIG. 1, when the flash memory is programmed to 01 state from 00 state, the gate voltage Vg initially at 5 volts, and ΔVg of 0.1 volt, the source voltage of ground, and the drain voltage Vd of 4.5±0.25 volt are shot 20 times. When the flash memory is programmed to 10 state from 00 state, the gate voltage Vg initially at 5 volts, and ΔVg of 0.1 volt, the source voltage of ground, and the drain voltage Vd of 4.5±0.25 volt are shot for 40 times. When the flash memory is programmed to 11 state from 00 state, the gate voltage Vg initially at 5 volts, and ΔVg of 0.1 volt, the source voltage of ground, and the drain voltage Vd of 4.5±0.25 volt are shot for 60 times. In addition to the different number of shot times respectively corresponding to the different states, the last gate voltage Vg shot is the program verify voltage PV, and all the shots including the second to last Vg shot before the very last shot is the program voltage PGM.
When the flash memory performs an erase operation from 01 or 10 or 11 state to 00 state, the source voltage Vs and the bulkvolt Vb of +8±0.25 volt , the gate voltage Vg initially −6 volts with ΔVg is −0.5 volt are shot 5 times.
FIG. 2A and FIG. 2B show the distribution of the reading current Ir and the initial voltage Vt when the programming and erasing of the flash memory are finished and the flash memory state is determined. During programming of the multi-flash memory, if the sense margin in each tracking of the reading current is not high enough misjudgments of the multi-flash memory will easily occur. The problem is more likely to happen at the lowest state or highest state. As shown in FIG. 2A, the tracking of the reading current Ir is distributed in all the 00, 01, 10 and 11 states, and the reliability interval exists in between the tracking of the reading current Ir. The sense margin of each state comprises the partial range of the corresponding tracking of the reading current Ir. The reliability interval for separating each tracking of the reading current Ir is quite narrow. Furthermore, the reliability interval also limits the increase of the sense margin, and so engenders errors, especially when the flash memory is in 00 or 11 state. In FIG. 2B, the voltage interval of the operation initial voltage Vt for determining the state of the flash memory is also too narrow, so as to easily engender errors especially when the flash memory is in 00 or 11 state.